Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), have been used to increase the data processing speed for various computing applications requiring high performance. Such applications have some functions implemented as software that executes on a processor (“software functions”) and other functions implemented as circuits on a PLD (“hardware functions”). A performance increase is achieved from functions being performed much faster as circuits than those functions could be performed as software.
The ability to specify both the software functions and hardware functions of a high-performance computing application in a high-level language (HLL) such as C, C++, or Java, for example, significantly simplifies the task of the application designer since many of the implementation details of the underlying PLD may be hidden from the designer. In combination with known compilers, a tool such as that described in U.S. Pat. No. 7,315,991, entitled “Compiling HLL into Massively Pipelined Systems,” by Bennett, may be used to develop and implement a high-performance computing application with hardware functions on a PLD. The Bennett approach generates a data-driven pipelined system for implementation on a PLD.
The interdependency of the software functions and hardware functions on data accessed by the functions, in combination with the differences between a microprocessor memory model and a data driven model, may limit the effectiveness of implementing some of the functions from the HLL program as hardware functions. Generally, in a microprocessor memory model, input data to be operated by a microprocessor is available for access according to a memory hierarchy: non-volatile memory, volatile RAM, and one or more levels of cache. In contrast, in a data driven model, the data to be operated on by a circuit in the pipeline is generally not available for random access. Rather, the data arrives sequentially in one or more data streams. In some instances, the data dependencies between the hardware and software functions may cause those functions to have to wait for data.
The present invention may address one or more of the above issues. The following paragraphs are provided as background for PLDs on which hardware functions may be implemented.
PLDs are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles may include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that may include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these example devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.